Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth. Of note, as used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
FPGAs have been used to accelerate applications. For example, FPGAs have been used in high-performance computing environments, among other known applications, where the FPGA architecture may be used to implement significantly pipelined systems. As used herein, by pipelined systems, it is generally meant a circuit involving at least one pipeline in which data is processed as one or more data streams. Thus, FPGA architectures may be used to build application-specific machines to execute many operations in parallel.
Conventionally, the data streaming model is used by FPGA application developers in their hardware compilation flow. Such a compilation flow conventionally involves an understanding of the circuitry to be implemented in programmable logic. For example, for a data streaming application, data in memory may be read out sequentially such that data may be continuously read and fed to a pipeline for processing. Such sequential reads of data may involve scheduling, which may involve a fairly in-depth understanding of operating parameters of the circuit to be implemented in programmable logic of the FPGA.
In contrast to the hardware compilation flow conventionally used for FPGAs, a programming model for microprocessors conventionally does not involve such an in-depth understanding of the operation of the processor. Moreover, software engineers may specify instructions to be carried out by a processor or processors using a high level language (“HLL”). Examples of such HLLs are C, C++, FORTRAN, and Java, among others. After a software engineer has written source code for an application to be carried out by a processor or processors, the application is conventionally compiled and debugged with a debugger. The compiled application may be assembled by an assembler to provide machine level language code. Of note, each of these operations may be performed within a software development environment, separate from the hardware development environment associated with programming FPGAs.
In order to exploit parallelism capable of being implemented in an FPGA, software engineers converted from the software development environment to the hardware development environment in order to transition from the programming model to the hardware model. This conversion involved an in-depth understanding of the circuits' operation by the software engineer and was often a very daunting task. In order to use an HLL source code to generate a configuration bitstream for an FPGA, HLL source code was compiled using compilers that are adapted for providing circuits following the data streaming model. Thus, for HLL source code written with a microprocessor memory model in mind, this meant converting the HLL source code to a data streaming model suitable for use with such compilers. Generally, in a microprocessor memory model, input data to be operated by a microprocessor is available for random access from disk or memory. This is a more conventional stored relation model for example as between microprocessor and memory. In contrast, in a data streaming model, some or all input data to be operated on by a circuit operator is not available for random access, but rather arrives sequentially as one or more continuous data streams.
Accordingly, it would be desirable and useful to provide means to transition a programming model more smoothly to provide a description of circuits that may be implemented in an FPGA without having to substantially convert an application from the programming model to a data streaming model.